Increase in the speed of information processing in a computer, a mobile communication device, and the like matches the trend aiming at so-called ubiquitous computing and is becoming more and more important. It accompanies strong demand for development of a higher-speed nonvolatile memory. As a memory replacing a conventional flash EEPROM, a hard disk device, and the like, an MRAM (Magnetic Random Access Memory) is regarded as a promising memory.
In the MRAM, each of memory cells arranged in a matrix is constructed by a magnetic device. The MRAM currently used in practice utilizes the giant magneto-resistive (GMR) effect. The GMR effect is a phenomenon such that in a stacked body in which two ferromagnetic layers are disposed so that their axes of easy magnetization are aligned, in the case where the magnetization directions of the layers are parallel with the axis of easy magnetization, the resistance value of the stacked layer becomes the minimum. In the case where the magnetization directions are anti-parallel with the axis of easy magnetization, the resistance value becomes the maximum. In each of the memory cells, by making the two states correspond to binary information of “0” and “1”, information is stored. By detecting the resistance which varies according to information as a change in current or voltage, information is read. In an actual GMR device, two ferromagnetic layers are stacked sandwiching a nonmagnetic layer. One of the two ferromagnetic layers is a pinned layer whose magnetization direction is pinned, and the other is a free layer (magneto-sensitive layer) whose magnetization direction can change according to an external magnetic field.
On the other hand, in a magnetic device using a tunneling magneto-resistive (TMR) effect, the resistance change rate can be made much higher than that of the GMR device. The TMR effect is a phenomenon such that the value of tunnel current passing through an insulating layer changes in accordance with relative angles of the magnetization directions of two ferromagnetic layers (a pinned layer and a free layer) stacked while sandwiching a very-thin insulating layer. That is, the tunnel current becomes the maximum (the resistance value of the device is the minimum) when the magnetization directions of the two ferromagnetic layers are parallel with each other, and becomes the minimum (the resistance value of the device is the maximum) when the magnetization directions are anti-parallel with each other. Based on the principle, there is a TMR device whose resistance change rate reaches 40% or higher. Since the resistance of the TMR device is high, it is said that matching with MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is easy. From the above advantages, the TMR-MRAM can easily obtain a higher output, and improvement in storage capacity and access speed is expected.
Those MRAMs write information by similar methods although their types of elements are different from each other. Specifically, current is passed to a write line to introduce a magnetic field, and the magnetization direction of the free layer is controlled by the current magnetic field. By the control, the relative magnetization directions of the ferromagnetic layers become parallel or anti-parallel with each other, and corresponding binary information is stored.
For example, a conventional TMR-MRAM has the following configuration. As shown in FIG. 24, a bit line 201 and a write word line 202 extending linearly are orthogonal to each other. In an area of a dotted line using, as a unit, a TMR device 205 (expressed as a resistor in the circuit) disposed at each of the intersecting areas of the bit line 201 and the write word line 202, a memory cell is constructed. The bit line 201 is a line commonly used for writing and reading, functions as a cell selection line in the bit direction at the time of writing, and functions as a sense line at the time of reading. To each of the bit lines 201, the source and drain of a bit selecting transistor 204 are connected. Current flows to the bit line 201 only when the bit line 201 is selected by a bit decode value input to the gate terminal. Similarly, current flows to the write word line 202 only when the write word line 202 is selected according to a word decode value. Therefore, in a selected cell at the time of writing, current flows in both of the bit line 201 and the write word line 202.
For reading operation, one end of the TMR device 205 is connected to the bit line 201, and the other end is grounded via a cell selecting transistor 206. The gate terminal of the cell selecting transistor 206 is connected in parallel with a read word decode line 203 provided for each cell word line. Therefore, in a selected cell at the time of reading, sensing current supplied from the bit line 201 passes through the TMR device 205 and the cell selecting transistor 206 and flows to the ground.
FIG. 25 shows a sectional structure of a memory cell seen from the direction of the arrow A in FIG. 24. The TMR device 205 is a stacked body of a pinned layer 207, an insulating layer 208, and a free layer 209. The magnetization of the pinned layer 207 is fixed in the direction shown in the diagram, and the magnetization of the free layer 209 can be inverted in both of the directions shown in the diagram. A write state of the TMR device 205 is determined by the relative magnetization directions of the free layer 209 and the pinned layer 207, that is, the magnetization direction of the free layer 209. However, conventionally, at the time of writing, current is passed to the bit line 201 and the write word line 202 to induce the magnetic fields into two directions to the free layer 209.
The operation is based on the theory of switching magnetic fields, in which when a synthetic magnetic field vector of magnetic fields Hx and Hy exceeds the region specified by a closed curve (so-called asteroid curve) shown in FIG. 26, the magnetization direction of the free layer 209 can be changed by the synthetic magnetic field. The free layer 209 in this case is a thin film having uniaxial magnetic anisotropy and has a single magnetic domain structure. It is assumed that magnetization inversion occurs by simultaneous turn. The magnetic fields Hx and Hy are magnetic field components in the direction of the axis of hard magnetization and the direction of the axis of easy magnetization of the free layer 209. When the synthetic magnetic field is applied in the direction at the angle φ with respect to the axis of easy magnetization in the film surface of the free layer 209, the magnetization is at the angle satisfying 0<θ<φ at which torque received from the magnetic field and torque toward the axis of easy magnetization by magnetic anisotropy are equal to each other. The critical magnetic field in magnetization switching is expressed by the curve of FIG. 26 (Hsw denotes the threshold of the application magnetic field which enables magnetization inversion). The process of specifying each of the directions of matrix electrode wiring by inputting an address and unconditionally selecting a desired cell is according to the principle of the matrix driving method.
In the matrix driving method, generally, auxiliary cell selection that makes a predetermined cell line half-selected is performed by using a selection line. By giving a data signal exceeding an operation threshold to a data line, a single cell is selected from the half-selected cells. The state is controlled according to data. Memories other than the MRAM and a digitally-driven display are also designed on the basis of such an operation principle. With respect to this point as well, a conventional MRAM is not exceptional but is driven based on a similar principle. Specifically, current is passed in the direction of blank arrows in FIGS. 24 and 25 to the bit line 201 to make the bias magnetic fields Hx generate in a predetermined direction, and a corresponding bit line is half-selected. On the other hand, current is passed in the direction according to data out of the both directions to the write word line 202 to make the magnetic fields Hy or the inversion magnetic fields −Hy corresponding to the magnetization direction of the free layer 209 generate. In such a manner, the magnetization direction control according to data is selectively performed on a cell in the corresponding word line in the half-selected bit line.
Since the bit line 201 is used for detecting weak voltage or current as a sense line at the time of reading, it is designed as a common line whose current permission value is small. The amount of current passed at the time of writing is also small. That is, the magnetic field Hx is relatively small and is regarded as a bias magnetic field whose direction is fixed and which is applied for selecting a cell.
On the other hand, in recent years, cell structures aiming at improvement in write efficiency have been proposed. For example, as shown in FIG. 27, a technique of introducing a closed magnetic circuit structure to a memory cell 211 to reduce the influence of a demagnetizing field at an end of a free layer 214 and stabilize the magnetization of the memory cell 211 is disclosed (refer to Japanese Patent Laid-Open No. 2001-273759). The memory cell 211 has a pinned layer 212, an insulating layer 213, the free layer 214, and a closed magnetic circuit layer 215 which are stacked. The closed magnetic circuit layer 215 promotes magnetization inversion of the free layer 214 and also contributes to stabilize the magnetization against an external leak magnetic field. Therefore, reduction in size of the memory cell 211 can be realized. For example, a technique of bending write lines as shown in FIG. 28 to shorten the minimum cycle of the write lines, thereby realizing higher packing density is proposed. In the diagram, a word line 217 has a linear shape and a bit line 216 is bent.
A similar wiring structure is also disclosed in Japanese Patent Laid-Open No. 2002-289807 (FIG. 29). In this case, a write line 221 is bent with a wiring width of “a” and a bent-portion length of “b”, and the relative directions of write current flowing in the portion and write current in the write line 222 are controlled. In such a manner, as shown in FIG. 30, an induced magnetic field H1 by the write current in the write line 221 is generated at an angle θ=tan−1 (b/a) relative to an induced magnetic field H2 by the write current in the write line 222 in order to make a resultant vector H12 of the magnetic fields H1 and H2 larger than that in the case where the magnetic fields are orthogonal to each other.
The inventors of the present invention, however, have noticed that if a conventional wiring structure and a convention writing method are employed in the case of disposing write lines in the memory cells almost parallel to each other as described above, there is the possibility that reliable writing is not performed.
In a conventional MRAM circuit, since it is necessary to pass write current in the inverted direction in accordance with data to the write word line 202, by giving a positive pulse or negative pulse, current can be passed in both directions. In contrast, to the bit line 201, write current is supplied only in one direction to give the fixed bias magnetic field Hy. Moreover, the bit line 201 has the structure in which current can be passed always only in one direction (the direction of the blank arrows in FIGS. 24 and 25).
If a negative pulse voltage is applied to the bit line 201 to pass current in the direction opposite to that shown by the blank arrow in FIG. 24, the current passes through the cell selection transistor 206 of each of cells connected to the bit line 201. Specifically, the cell selection transistor 206 is generally an enhancement-mode MOS transistor and the gate voltage of the cell selection transistor 206 in an off state for writing operation is supposed to be 0V or negative potential at this time. If the negative pulse is applied to the drain side in this case, since the gate has the same potential of 0V as that on the source side or a higher potential, the inherent function of the source and that of the drain are reversed, and current flows from the source to the drain.
When the magnetic fields H1 and H2 are applied as shown in FIG. 30 by applying such a conventional circuit configuration and a conventional driving method, as shown in FIG. 31, an inverted magnetic field vector −H12 obtained by the magnetic fields H1 and −H2 is not symmetrical with the magnetic field vector H12 with respect to the axis of easy magnetization of the free layer 209, and the magnitude of the inverted magnetic field vector −H12 is smaller than that of the magnetic field vector H12. Consequently, binary information cannot to be written in an equivalent state and, moreover, there is the possibility that binary information cannot be written reliably.
As described above, even if the structure of the write line is improved, when the improved structure is simply fit in a conventional circuit configuration, the resultant structure cannot be practically used. On the other hand, under present circumstances, improvement in a whole configuration of a circuit has not been progressed and the configuration of the MRAM and the principle of driving have not been largely changed from the conventional ones. In view of the circumstances, the inventors of the present invention have concluded that it is necessary to improve an MRAM as a memory which can be actually driven and, for this purpose, to improve not only a write line in a conventional circuit but also a whole memory structure including a read circuit system in order to achieve the object.